Digital phase-locked loops (DPLLs) are a viable alternative to traditional PLLs, in which a digital loop filter can be utilized to replace analog components. DPLLs can provide a low-power-space solution relative to old fashion analog phase-locked loops (PLLs). In DPLL architectures for oscillator generation, a phase offset between a local oscillator (LO) and a reference clock is measured using an analog to digital converter such as a time-to-digital converter (TDC). A measured phase is compared to a required phase and the result is used to correct the LO frequency. As a result of a conversion to the digital domain, the phase measurements can suffer from quantization errors, which then become inserted into a control loop of the DPLL and limit the DPLL Phase-Noise (PN) performances. Solutions to overcome or further reduce the quantization errors of DPLLs without increasing power consumption or further complicating circuit designs would increase the viability of DPLLs as desired operational components for oscillator generation.